Usually in the form of parallel processing with parallel multi-processor systems are designed. For this reason irregular flow may occur with packages. When you' re tired and it all comes out in his NP (NETWORK PROCESSORS) system, Reset depending on NETWORK performance is negatively affected and we delayed To do this, The design of PROCESSORS working in parallel packet transmission by avoiding any packet reordering occur, If reordering, this time delay is minimal. Several algorithms have been proposed in recent years. In this paper, we will describe some of the fundamental concepts involved in NP architecture and algorithms packet reordering in recent years, which causes delays are minimized packet reordering, the evaluation will be compared.

Voltage scaling is a widely used technique for energy saving, which increases the delay in the NETWORK in MPSoCs. To overcome this challenge, the volume of communication in the NETWORK should be reduced. In memory-intensive and communication-intensive applications, a considerable part of the NETWORK delay is due to the traffic originated from cache misses. In this paper, we employ the voltage scaling method in an adaptive way, while the free space of the NoC input buffers is used to reduce the traffic caused by the cache misses. Therefore, the proposed method increases the memory efficiency and reduces the energy consumption of the chip. To have an adaptive approach, the voltage is adjusted according to the average amount of free space of the NoC buffers, and the voltage scaling stops when the buffers are close to full. We achieve a 16% reduction in miss penalty on average, and a 12.5% improvement in power consumption.

when an architect confronts a new design problem he uses a sophisticated and unclear process to find the solution. Clarifying the process for an action-oriented activity such as architecture is not an easy task. The process could be quit different for each architect and each subject. This is a reason why most of the design.process models are descriptive instead of prescriptive. The stage of finding the main idea or concept of an architectural design - that is the point of the relation of theory and practice in my opinion - is an unknown stage. In the beginning of the 20th century, it was argued that the creative process could be segmented into four successive stages. Wallas drawing on the observations of Helmholtz labeled these stages preparation, incubation, illumination, and verification.Main idea that is the result of illumination can be named primary generator. Jane Darke-through her PhD thesis on the supervision of Lawson - brings "Primary Generator" to the literature of design research domain for the first time. Darke found that the architects latched on to a relatively simple idea early on, and that the idea would then narrow down the space of possible solutions by providing an initial focus Le. by constraining and guiding the designer's development of a solution. Lawson on his book entitled "How Designers Think" developed "Primary Generators". He observed that some designers deliberately generate a series of alternative primary generators, followed by progressive refinement, testing and selection. Attfield, Blandford, and Dowell on their paper entitled of "Information seeking in the Context of Writing" and Sharples on his paper "An Account of Writing as Creative Design" developed Primary generators' territory to toner' domains such as journalism and writing., - The role of primary generators in architectural design process requires a closer look. So, this paper attempt to concentrate on it. It explores the ~differentiation aspects of generators and PROCESSORS in design. Then we try finding a model that shows the role of them in design process. On the second part of this paper, the approaches of architects to use different primary generators would be discussed. These approaches categorized in two parts: "formal-objective" and "conceptual-subjective". Paper gives some examples for each of these parts through reviewing the design process of famous architects. Processor of design and its role through design process is also discussed. In this paper three PROCESSORS' category is distinguished: processor as developer, processor as critic, and processor as controller.On the last part of this paper a model is drawn that shows the role of primary generators and design PROCESSORS through design. It describes the effect of architect's background on the generator and PROCESSORS which he adopting.

Increasing the number of processor cores leads to increasing the density of the computing power processor and also raising the temperature. Temperature management is very important in these PROCESSORS. Thermal management methods are introduced to reduce the CPU temperature. Reactive and proactive approaches are two sets of these schemes. Unlike the reactive techniques, proactive methods predict the temperature using thermal prediction model before reaching its threshold. In this paper, a hybrid model of several SVR models is proposed for predicting temperature. An appropriate dataset is created for training proposed model that includes a high diversity of processor temperature variations. Some features of dataset are measured using temperature sensors and system performance counters. Other features, with historical and control names are calculated with the proposed processes to increase the accuracy of thermal model. Two SVR models are used in the proposed thermal model to reduce its operational overhead. The proper features for each SVR model are selected by the feature selection algorithm based on mutual information. The proposed model is evaluated for temperature prediction for 2 to 5 time distances. The results show that with a selection of 11 features for thermal prediction model of the next 2 seconds, the mean absolute error is about 0.5oC.

Today’s multi-core PROCESSORS are built by all processor manufacturers for computers, cell phones, and other embedded systems. For all computer engineers, designing and researching the hardware architecture of multicore systems is critical. The type of cache coherence protocol employed on a multi-core computer has a direct impact on execution time, latency, and power consumption. Because it is a good example of a CPU, a 32-bit MIPS processor was chosen. With the addition of our prior work, an advanced special circuit was created using VHDL coding and ISE Xilinx software to implement it. One protocol was utilized in this design, the MOESI (Modify, Owned, Exclusive, Shared, and Invalid) protocol. The result of the test was obtained using a test bench, and they revealed that all of the protocols’ states were operational.